"Post-layout timing simulation of CMOS circuits."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

Denis Deschacht et al. (1993)

> Home

Details and statistics

DOI: 10.1109/43.238609

access: closed

type: Journal Article

metadata version: 2022-10-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcad/DeschachtRAA93
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcad/DeschachtRAA93
Denis Deschacht, Michel Robert, Nadine Azémard-Crestani, Daniel Auvergne:
Post-layout timing simulation of CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(8): 1170-1177 (1993)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.