"Techniques for minimizing power dissipation in scan and combinational ..."

Vinay Dabholkar et al. (1998)

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DOI: 10.1109/43.736572

access: closed

type: Journal Article

metadata version: 2020-09-24

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Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy:
Techniques for minimizing power dissipation in scan and combinational circuits during test application. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(12): 1325-1333 (1998)

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