"Floorplet: Performance-Aware Floorplan Framework for Chiplet Integration."

Shixin Chen et al. (2024)

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DOI: 10.1109/TCAD.2023.3347302

access: closed

type: Journal Article

metadata version: 2024-08-04

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Shixin Chen, Shanyi Li, Zhen Zhuang, Su Zheng, Zheng Liang, Tsung-Yi Ho, Bei Yu, Alberto L. Sangiovanni-Vincentelli:
Floorplet: Performance-Aware Floorplan Framework for Chiplet Integration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(6): 1638-1649 (2024)

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