"Timing analysis speed-up using a hierarchical and a multimode approach."

Yves Blaquière, Michel R. Dagenais, Yvon Savaria (1996)

> Home

Details and statistics

DOI: 10.1109/43.486669

access: closed

type: Journal Article

metadata version: 2022-06-13

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcad/BlaquiereDS96
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcad/BlaquiereDS96
Yves Blaquière, Michel R. Dagenais, Yvon Savaria:
Timing analysis speed-up using a hierarchical and a multimode approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(2): 244-255 (1996)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.