"Towards a Verification Flow Across Abstraction Levels Verifying ..."

Pablo González de Aledo et al. (2017)

> Home

Details and statistics

DOI: 10.1109/TCAD.2016.2611494

access: closed

type: Journal Article

metadata version: 2020-09-24

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcad/AledoPWDS17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcad/AledoPWDS17
Pablo González de Aledo, Nils Przigoda, Robert Wille, Rolf Drechsler, Pablo Sánchez Espeso:
Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal Specification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(3): 475-488 (2017)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.