"A Layout System for the Random Logic Portion of an MOS LSI Chip."

Isao Shirakawa et al. (1981)

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DOI: 10.1109/TC.1981.1675842

access: closed

type: Journal Article

metadata version: 2017-05-20

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Isao Shirakawa, Noboru Okuda, Takashi Harada, Sadahiro Tani, Hiroshi Ozaki:
A Layout System for the Random Logic Portion of an MOS LSI Chip. IEEE Trans. Computers 30(8): 572-581 (1981)

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