"On Polynomial-Time Testable Combinational Circuits."

Nageswara S. V. Rao, Shunichi Toida (1994)

> Home

Details and statistics

DOI: 10.1109/12.324562

access: closed

type: Journal Article

metadata version: 2017-06-08

- view
  authority control:
- export record
  dblp key:
  - journals/tc/RaoT94
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tc/RaoT94
Nageswara S. V. Rao, Shunichi Toida:
On Polynomial-Time Testable Combinational Circuits. IEEE Trans. Computers 43(11): 1298-1308 (1994)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.