"Simulation of a Horizontal Bit-Sliced Processor Using the ISPS ..."

Andries van Dam et al. (1981)

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DOI: 10.1109/TC.1981.1675830

access: closed

type: Journal Article

metadata version: 2017-05-20

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Andries van Dam, Mario Barbacci, Constantine Halatsis, J. Joosten, M. Letheren:
Simulation of a Horizontal Bit-Sliced Processor Using the ISPS Architecture Simulation Facility. IEEE Trans. Computers 30(7): 513-519 (1981)

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