"A New Parallel Algorithm for Time-Slot Assignment in Hierarchical ..."

Suresh Chalasani (1997)

> Home

Details and statistics

DOI: 10.1109/12.641940

access: closed

type: Journal Article

metadata version: 2017-05-20

- view
  authority control:
- export record
  dblp key:
  - journals/tc/Chalasani97
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tc/Chalasani97
Suresh Chalasani:
A New Parallel Algorithm for Time-Slot Assignment in Hierarchical Switching Systems. IEEE Trans. Computers 46(12): 1387-1395 (1997)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.