"VLSI implementation issues for the 2-D Fermat number transform."

M. Benaissa, Satnam Singh Dlay, A. G. J. Holt (1991)

> Home

Details and statistics

DOI: 10.1016/0165-1684(91)90004-3

access: closed

type: Journal Article

metadata version: 2020-02-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/sigpro/BenaissaDH91
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/sigpro/BenaissaDH91
M. Benaissa, Satnam Singh Dlay, A. G. J. Holt:
VLSI implementation issues for the 2-D Fermat number transform. Signal Process. 23(3): 257-272 (1991)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.