"FPGA implementation of a Cholesky algorithm for a shared-memory ..."

Satchidanand G. Haridas, Sotirios G. Ziavras (2004)

> Home

Details and statistics

DOI: 10.1080/10637190412331279957

access: closed

type: Journal Article

metadata version: 2017-06-08

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/paapp/HaridasZ04
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/paapp/HaridasZ04
Satchidanand G. Haridas, Sotirios G. Ziavras:
FPGA implementation of a Cholesky algorithm for a shared-memory multiprocessor architecture. Parallel Algorithms Appl. 19(4): 211-226 (2004)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.