![](https://dblp.uni-trier.de./img/logo.320x120.png)
![search dblp search dblp](https://dblp.uni-trier.de./img/search.dark.16x16.png)
![search dblp](https://dblp.uni-trier.de./img/search.dark.16x16.png)
default search action
"V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator ..."
Chao Wang et al. (2024)
- Chao Wang
, Yicong Shao, Jiajie Huang
, Wangzilu Lu
, Zhiwen Gu
, Longfan Li
, Yuhang Zhang
, Jian Zhao
, Wei Mao, Yongfu Li
:
V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation. IEEE Open J. Circuits Syst. 5: 387-397 (2024)
![](https://dblp.uni-trier.de./img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.