"A Power Efficiency Enhancements of a Multi-Bit Accelerator for Memory ..."

Suhas Shivapakash et al. (2021)

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DOI: 10.1109/OJCAS.2020.3047225

access: open

type: Journal Article

metadata version: 2021-07-29

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  - https://dblp.org/rec/journals/ojcands/ShivapakashJHG21
Suhas Shivapakash, Hardik Jain, Olaf Hellwich, Friedel Gerfers:
A Power Efficiency Enhancements of a Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks. IEEE Open J. Circuits Syst. 2: 156-169 (2021)

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