"An FPGA Hardware Parallel Implementation of the DES Algorithm."

I. N. Tselepis, Michael P. Bekakos (2004)

> Home

Details and statistics

DOI: —

access: unavailable

type: Journal Article

metadata version: 2023-08-04

- no documents available
- export record
  dblp key:
  - journals/npsc/TselepisB04
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/npsc/TselepisB04
I. N. Tselepis, Michael P. Bekakos:
An FPGA Hardware Parallel Implementation of the DES Algorithm. Neural Parallel Sci. Comput. 12(4): 455-464 (2004)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.