"Single event double node upset tolerance in MOS/spintronic sequential and ..."

Ramin Rajaei (2017)

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DOI: 10.1016/J.MICROREL.2016.12.003

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type: Journal Article

metadata version: 2020-02-22

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Ramin Rajaei:
Single event double node upset tolerance in MOS/spintronic sequential and combinational logic circuits. Microelectron. Reliab. 69: 109-114 (2017)

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