"Barrier layer thickness analysis for reliable copper plug process in CMOS ..."

S. K. Manhas, N. Singh, G. Q. Lo (2011)

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DOI: 10.1016/J.MICROREL.2011.03.005

access: closed

type: Journal Article

metadata version: 2020-02-22

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S. K. Manhas, N. Singh, G. Q. Lo:
Barrier layer thickness analysis for reliable copper plug process in CMOS technology. Microelectron. Reliab. 51(8): 1365-1371 (2011)

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