"Impact of gate stack process on conduction and reliability of 0.18 mum ..."

G. Ghidini et al. (2003)

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DOI: 10.1016/S0026-2714(03)00175-6

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type: Journal Article

metadata version: 2022-10-02

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G. Ghidini, A. Garavaglia, G. Giusto, Andrea Ghetti, R. Bottini, D. Peschiaroli, M. Scaravaggi, F. Cazzaniga, Daniele Ielmini:
Impact of gate stack process on conduction and reliability of 0.18 mum PMOSFET. Microelectron. Reliab. 43(8): 1221-1227 (2003)

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