"Impact of floorplanning and thermal vias placement on temperature in 2D ..."

Piotr Zajac et al. (2016)

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DOI: 10.1016/J.MEJO.2016.02.013

access: closed

type: Journal Article

metadata version: 2020-10-26

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Piotr Zajac, Melvin Galicia, Cezary Maj, Andrzej Napieralski:
Impact of floorplanning and thermal vias placement on temperature in 2D and 3D processors. Microelectron. J. 52: 40-48 (2016)

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