"A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on ..."

Mingche Lai et al. (2022)

> Home

Details and statistics

DOI: 10.1016/J.MEJO.2022.105628

access: closed

type: Journal Article

metadata version: 2024-01-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/mj/LaiZLZWLXQ22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/mj/LaiZLZWLXQ22
Mingche Lai, Geng Zhang, Fangxu Lv, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi:
A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS. Microelectron. J. 130: 105628 (2022)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.