"Device and Circuit Level Design, Characterization and Implementation of ..."

B. V. V. Satyanarayana, Matta Durga Prakash (2020)

> Home

Details and statistics

DOI: 10.1016/J.MICPRO.2020.103164

access: closed

type: Journal Article

metadata version: 2020-10-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/mam/SatyanarayanaP20
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/mam/SatyanarayanaP20
B. V. V. Satyanarayana, Matta Durga Prakash:
Device and Circuit Level Design, Characterization and Implementation of Low Power 7T SRAM Cell using Heterojunction Tunneling Transistors with Oxide Overlap. Microprocess. Microsystems 77: 103164 (2020)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.