"Decimal addition on FPGA based on a mixed BCD/excess-6 representation."

Horácio C. Neto, Mário P. Véstias (2017)

> Home

Details and statistics

DOI: 10.1016/J.MICPRO.2017.10.004

access: closed

type: Journal Article

metadata version: 2022-12-07

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/mam/NetoV17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/mam/NetoV17
Horácio C. Neto, Mário P. Véstias:
Decimal addition on FPGA based on a mixed BCD/excess-6 representation. Microprocess. Microsystems 55: 91-99 (2017)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.