"A 0.016 mm2 0.26- $\mu$ W/MHz 60-240-MHz Digital PLL With ..."

Junheng Zhu, Woo-Seok Choi, Pavan Kumar Hanumolu (2019)

> Home

Details and statistics

DOI: 10.1109/JSSC.2019.2915021

access: closed

type: Journal Article

metadata version: 2020-08-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/ZhuCH19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/ZhuCH19
Junheng Zhu, Woo-Seok Choi, Pavan Kumar Hanumolu:
A 0.016 mm² 0.26- $\mu$ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS. IEEE J. Solid State Circuits 54(8): 2186-2194 (2019)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.