"A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic ..."

Jinn-Shyan Wang et al. (2015)

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DOI: 10.1109/JSSC.2015.2466443

access: closed

type: Journal Article

metadata version: 2020-08-30

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Jinn-Shyan Wang, Chun-Yuan Cheng, Pei-Yuan Chou, Tzu-Yi Yang:
A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture. IEEE J. Solid State Circuits 50(11): 2635-2644 (2015)

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