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"A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and ..."

Takashi Toi et al. (2022)

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DOI: 10.1109/JSSC.2021.3138797

access: closed

type: Journal Article

metadata version: 2022-05-18

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Takashi Toi, Junji Wadatsumi, Hiroyuki Kobayashi, Yutaka Shimizu, Yuji Satoh, Makoto Morimoto, Rui Ito, Mitsuyuki Ashida, Yuta Tsubouchi, Mai Nozawa, Go Urakawa, Jun Deguchi, Ryuichi Fujimoto:
A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems. IEEE J. Solid State Circuits 57(5): 1517-1526 (2022)

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