Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID"A 16 MHz BW 75 dB DR CT ΔΣ ADC Compensated for More Than One ..."
Vikas Singh et al. (2012)
- Vikas Singh, Nagendra Krishnapura
, Shanthi Pavan, Baradwaj Vigraham, Debasish Behera, Nimit Nigania:
A 16 MHz BW 75 dB DR CT ΔΣ ADC Compensated for More Than One Cycle Excess Loop Delay. IEEE J. Solid State Circuits 47(8): 1884-1895 (2012)
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2020-08-30 00:13 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
