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"A 32-Mb chain FeRAM with segment/stitch array architecture."
Shinichiro Shiratake et al. (2003)
- Shinichiro Shiratake, Tadashi Miyakawa, Yoshiaki Takeuchi, Ryu Ogiwara, Masahiro Kamoshida, Katsuhiko Hoya, Kohei Oikawa, Tohru Ozaki, Iwao Kunishima, Koji Yamakawa, Shigeki Sugimoto, Daisaburo Takashima, Hans-Oliver Joachim, Norbert Rehm, Joerg Wohlfahrt, Nicolas Nagel, Gerhard Beitel, Michael Jacob, Thomas Roehr:
A 32-Mb chain FeRAM with segment/stitch array architecture. IEEE J. Solid State Circuits 38(11): 1911-1919 (2003)
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