"Low-power synchronous-to-asynchronous- to-synchronous interlocked ..."

Stanley Schuster, Peter W. Cook (2003)

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DOI: 10.1109/JSSC.2003.809512

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type: Journal Article

metadata version: 2022-04-20

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Stanley Schuster, Peter W. Cook:
Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz. IEEE J. Solid State Circuits 38(4): 622-630 (2003)

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