"A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With ..."

Robert Reutemann et al. (2010)

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DOI: 10.1109/JSSC.2010.2077350

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type: Journal Article

metadata version: 2020-08-30

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Robert Reutemann, Michael Ruegg, Fran Keyser, John Bergkvist, Daniel Dreps, Thomas Toifl, Martin L. Schmatz:
A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS. IEEE J. Solid State Circuits 45(12): 2850-2860 (2010)

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