"The Circuits and Robust Design Methodology of the Massively Parallel ..."

Hideyuki Noda et al. (2007)

> Home

Details and statistics

DOI: 10.1109/JSSC.2007.891680

access: closed

type: Journal Article

metadata version: 2020-08-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/NodaTGDNMYINOA07
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/NodaTGDNMYINOA07
Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Katsumi Dosaka, Masami Nakajima, Katsuya Mizumoto, Kanako Yoshida, Takenobu Iwao, Tetsu Nishijima, Yoshihiro Okuno, Kazutami Arimoto:
The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture. IEEE J. Solid State Circuits 42(4): 804-812 (2007)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.