"Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% ..."

Sheyang Ning et al. (2016)

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DOI: 10.1109/JSSC.2016.2561966

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type: Journal Article

metadata version: 2020-08-30

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Sheyang Ning, Tomoko Ogura Iwasaki, Shuhei Tanakamaru, Darlene Viviani, Henry Huang, Monte Manning, Thomas Rueckes, Ken Takeuchi:
Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory. IEEE J. Solid State Circuits 51(8): 1938-1951 (2016)

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