"A 6.7-MFLOPS floating-point coprocessor with vector/matrix instructions."

Takashi Nakayama et al. (1989)

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DOI: 10.1109/JSSC.1989.572608

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type: Journal Article

metadata version: 2024-11-12

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Takashi Nakayama, Hisao Harigai, Shingo Kojima, Hiroaki Kaneko, Hatsuhide Igarashi, Tsuneo Toba, Yutaka Yamagami, Yoichi Yano:
A 6.7-MFLOPS floating-point coprocessor with vector/matrix instructions. IEEE J. Solid State Circuits 24(5): 1324-1330 (1989)

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