"2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor."

Fumio Murabayashi et al. (1996)

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DOI: 10.1109/4.508211

access: closed

type: Journal Article

metadata version: 2022-07-18

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  - https://dblp.org/rec/journals/jssc/MurabayashiYYNS96
Fumio Murabayashi, Tatsumi Yamauchi, Hiromichi Yamada, Takahiro Nishiyama, Kotaro Shimamura, Shigeya Tanaka, Takashi Hotta, Teruhisa Shimizu, Hideo Sawamoto:
2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor. IEEE J. Solid State Circuits 31(7): 972-980 (1996)

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