"A 25-ns 4-Mbit CMOS SRAM with dynamic bit-line loads."

Fumio Miyaji et al. (1989)

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DOI: 10.1109/JSSC.1989.572582

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type: Journal Article

metadata version: 2025-01-22

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Fumio Miyaji, Yasushi Matsuyama, Yoshikazu Kanaishi, Katsunori Seno, Takashi Emori, Yoshiaki Hagiwara:
A 25-ns 4-Mbit CMOS SRAM with dynamic bit-line loads. IEEE J. Solid State Circuits 24(5): 1213-1218 (1989)

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