"A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved ..."

Tatsuji Matsuura et al. (1998)

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DOI: 10.1109/4.726586

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type: Journal Article

metadata version: 2022-07-05

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Tatsuji Matsuura, Takashi Nara, Tatsuya Komatsu, Eiki Imaizumi, Toshihiro Matsutsuru, Ryutaro Horita, Haruto Katsu, Shintaro Suzumura, Kazuo Sato:
A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter. IEEE J. Solid State Circuits 33(11): 1840-1850 (1998)

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