"A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a ..."

Tatsuya Matano et al. (2003)

> Home

Details and statistics

DOI: 10.1109/JSSC.2003.810030

access: closed

type: Journal Article

metadata version: 2022-04-20

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/MatanoTTSFTFKNA03
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/MatanoTTSFTFKNA03
Tatsuya Matano, Yasuhiro Takai, Tsugio Takahashi, Yuusuke Sakito, Isamu Fujii, Yoshihiro Takaishi, Hiroki Fujisawa, Shuichi Kubouchi, Seiji Narui, Koji Arai, Makoto Morino, Masayuki Nakamura, Shinichi Miyatake, Toshihiro Sekiguchi, Kuniaki Koyama:
A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer. IEEE J. Solid State Circuits 38(5): 762-768 (2003)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.