"Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator ..."

John G. Maneatis et al. (2003)

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DOI: 10.1109/JSSC.2003.818298

access: closed

type: Journal Article

metadata version: 2022-04-20

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John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas:
Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL. IEEE J. Solid State Circuits 38(11): 1795-1803 (2003)

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