"A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital ..."

Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu (2005)

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DOI: 10.1109/JSSC.2005.845986

access: closed

type: Journal Article

metadata version: 2022-03-02

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Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu:
A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration. IEEE J. Solid State Circuits 40(5): 1047-1056 (2005)

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