"An Area-Efficient Low-Jitter Fractional Output Divider With ..."

Chun-Yu Lin et al. (2024)

> Home

Details and statistics

DOI: 10.1109/JSSC.2024.3399733

access: closed

type: Journal Article

metadata version: 2024-11-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/LinCHWL24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/LinCHWL24
Chun-Yu Lin, Wei-Han Chen, Yu-Ting Hung, Tun-Ju Wang, Tsung-Hsien Lin:
An Area-Efficient Low-Jitter Fractional Output Divider With Replica-DTC-Free Background Calibration. IEEE J. Solid State Circuits 59(11): 3705-3715 (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.