"A low-power 16×16-b parallel multiplier utilizing pass-transistor logic."

Chong-Fatt Law, Samir S. Rofail, Kiat Seng Yeo (1999)

> Home

Details and statistics

DOI: 10.1109/4.792613

access: closed

type: Journal Article

metadata version: 2023-06-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/LawRY99
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/LawRY99
Chong-Fatt Law, Samir S. Rofail, Kiat Seng Yeo:
A low-power 16×16-b parallel multiplier utilizing pass-transistor logic. IEEE J. Solid State Circuits 34(10): 1395-1399 (1999)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.