"A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability."

Patrik Larsson (1999)

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DOI: 10.1109/4.808920

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type: Journal Article

metadata version: 2022-07-05

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Patrik Larsson:
A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability. IEEE J. Solid State Circuits 34(12): 1951-1960 (1999)

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