"A 12 MHz data cycle 4 Mb DRAM with pipeline operation."

Natsuki Kushiyama et al. (1991)

> Home

Details and statistics

DOI: 10.1109/4.75042

access: closed

type: Journal Article

metadata version: 2025-02-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/KushiyamaWOMNF91
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/KushiyamaWOMNF91
Natsuki Kushiyama, Yohji Watanabe, Takashi Ohsawa, Kazuyoshi Muraoka, Yousei Nagahama, Tohru Furuyama:
A 12 MHz data cycle 4 Mb DRAM with pipeline operation. IEEE J. Solid State Circuits 26(4): 479-483 (1991)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.