"A 7-nm FinFET CMOS PLL With 388-fs Jitter and -80-dBc Reference Spur ..."

Chen-Ting Ko et al. (2020)

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DOI: 10.1109/JSSC.2019.2959735

access: closed

type: Journal Article

metadata version: 2020-08-30

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Chen-Ting Ko, Ting-Kuei Kuan, Ruei-Pin Shen, Chih-Hsien Chang:
A 7-nm FinFET CMOS PLL With 388-fs Jitter and -80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control. IEEE J. Solid State Circuits 55(4): 1043-1050 (2020)

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