"Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip ..."

Keiji Kishine, Kiyoshi Ishii, Haruhiko Ichino (2002)

> Home

Details and statistics

DOI: 10.1109/4.974544

access: closed

type: Journal Article

metadata version: 2022-04-04

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/KishineII02
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/KishineII02
Keiji Kishine, Kiyoshi Ishii, Haruhiko Ichino:
Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX. IEEE J. Solid State Circuits 37(1): 38-50 (2002)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.