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"A pipelined multiplier-accumulator using a high-speed, low-power static ..."

Shyh-Jye Jou et al. (1997)

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DOI: 10.1109/4.553190

access: closed

type: Journal Article

metadata version: 2022-07-07

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  - journals/jssc/JouCYS97
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  - https://dblp.org/rec/journals/jssc/JouCYS97
Shyh-Jye Jou, Chang-Yu Chen, En-Chung Yang, Chau-Chin Su:
A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design. IEEE J. Solid State Circuits 32(1): 114-118 (1997)

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