"A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense ..."

Koichiro Ishibashi et al. (1995)

> Home

Details and statistics

DOI: 10.1109/4.375969

access: closed

type: Journal Article

metadata version: 2023-05-03

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/IshibashiTKTYFHOSHNN95
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/IshibashiTKTYFHOSHNN95
Koichiro Ishibashi, Koichi Takasugi, Kunihiro Komiyaji, Hiroshi Toyoshima, Toshiaki Yamanaka, Akira Fukami, Naotaka Hashimoto, Nagatoshi Ohki, Akihiro Shimizu, Takashi Hashimoto, Takahiro Nagano, Takashi Nishida:
A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers. IEEE J. Solid State Circuits 30(4): 480-486 (1995)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.