"Low-power logic circuit and SRAM cell applications with silicon on ..."

Satoshi Inaba et al. (2006)

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DOI: 10.1109/JSSC.2006.874335

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type: Journal Article

metadata version: 2022-10-02

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Satoshi Inaba, Hajime Nagano, Kiyotaka Miyano, Ichiro Mizushima, Yasunori Okayama, Takahiro Nakauchi, Kazunari Ishimaru, Hidemi Ishiuchi:
Low-power logic circuit and SRAM cell applications with silicon on depletion Layer CMOS (SODEL CMOS) technology. IEEE J. Solid State Circuits 41(6): 1455-1462 (2006)

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