"A 14-bit digitally self-calibrated pipelined ADC with adaptive bias ..."

Kunihiko Iizuka et al. (2006)

> Home

Details and statistics

DOI: 10.1109/JSSC.2006.870788

access: closed

type: Journal Article

metadata version: 2021-10-15

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/IizukaMUD06
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/IizukaMUD06
Kunihiko Iizuka, Hirofumi Matsui, Masaya Ueda, Mutsuo Daito:
A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s. IEEE J. Solid State Circuits 41(4): 883-890 (2006)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.