"A 0.5-V 12-bit SAR ADC Using Adaptive Time-Domain Comparator With Noise ..."

Sung-En Hsieh, Chen-Che Kao, Chih-Cheng Hsieh (2018)

> Home

Details and statistics

DOI: 10.1109/JSSC.2018.2862880

access: closed

type: Journal Article

metadata version: 2020-08-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/HsiehKH18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/HsiehKH18
Sung-En Hsieh, Chen-Che Kao, Chih-Cheng Hsieh:
A 0.5-V 12-bit SAR ADC Using Adaptive Time-Domain Comparator With Noise Optimization. IEEE J. Solid State Circuits 53(10): 2763-2771 (2018)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.