"Fractional-N DPLL-Based Low-Power Clocking Architecture for 1-14 Gb/s ..."

Masum Hossain et al. (2017)

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DOI: 10.1109/JSSC.2017.2715160

access: closed

type: Journal Article

metadata version: 2020-08-30

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Masum Hossain, Waleed El-Halwagy, A. K. M. Delwar Hossain, Aurangozeb:
Fractional-N DPLL-Based Low-Power Clocking Architecture for 1-14 Gb/s Multi-Standard Transmitter. IEEE J. Solid State Circuits 52(10): 2647-2662 (2017)

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