"A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined ..."

Terry I. Chappell et al. (1991)

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DOI: 10.1109/4.98975

access: closed

type: Journal Article

metadata version: 2025-02-26

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Terry I. Chappell, Barbara A. Chappell, Stanley E. Schuster, James W. Allan, Stephen P. Klepner, Rajiv V. Joshi, Robert L. Franch:
A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture. IEEE J. Solid State Circuits 26(11): 1577-1585 (1991)

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